MAHIR AYDIN
Phone: (703)309-3196, E-mail: maydin@premieresys.com
EDUCATION
Colorado State University, Ft.
Collins, CO
Ph. D
candidate in Electrical Engineering, August 2003-December 2004, GPA: 3.82/4.00
M.S.
in Computer Science, June 2002.
B.S.
in Computer Engineering, June 2001
5-Year
Cumulative GPA: 3.77/4.00
Union College International Scholarship recipient,
1997-2001, Dean’s List, 1997-2001
COMPUTER SKILLS
Languages: Java, C++,
PHP, XML, SQL, UML, Assembly Language (Motorola 68xx and IBM z/900), MATLAB,
SPICE, UNIX Shell Scripting, VHDL, Verilog HDL.
Operating Systems: Windows Server
2000 and 2003, Linux, HP-UX, AIX, Solaris, Windows 98/2000/XP
Applications: Netbeans IDE, Altova XMLSpy, Apache, MySQL, Datatel Colleague, Rational Rose, Mentor Calibre, Design Architect and IC Station, Altera MaxPlus, Tanner EDA Tools,
Microsoft Office.
RELEVANT EXPERIENCE
Programmer/Analyst, Premiere Systems Support,
Developed
and tested Premiere Systems Support’s (PSS) Communication Service Provider
(CSP) software, which provides communication and transformation services
between different ERP software packages and databases. Created new XML data transport schemes for
new services and implemented XML parsing and creation using Java. Administered the business application servers
such as IIS 6.0, Apache, Tomcat, Microsoft Exchange, MySQL.
Provided custom web sites for report generation, help desk, and project
management services.
Research Assistant, Colorado State University, Ft. Collins,
Conducted
research on modeling the effects of soft event upsets, caused by high-energy
neutron strikes to a circuit node, on high-speed microprocessors. Additional research topics included process
variations and statistical design.
Assistant, Computer Science Department,
Configured, maintained and troubleshot Windows
workstations and printers in the Computer Science Department. Configured and
installed software on Linux, Solaris and Windows 2000 servers.
Summer Intern, IBM Enterprise Server
Division,
Updated
and modified the Architecture Verification Program Generator (AVPGEN) code (C
and C++) to include support for new mainframe instructions and new
features. Debugged
existing code using the Xldb debugger. Worked on REXX scripts to
automatically perform dynamic address translation for the z/900 architecture. Performed regression
testing on generated instruction sequences using the AVPGEN software.
Summer
Intern, IBM Enterprise Server Division,
Ported Arla (An open-source
AFS client) to Linux/390. Ported Jabber (An
open-source instant messaging server) to Linux/390. Modified make scripts to compile the source
libraries under Linux/390.
Intern,
Netas (A Subsidiary of Nortel Networks),
Assisted in designing Digital Line Interface to Firing
FPGA using Verilog HDL. Participated
on synthesis, placement and routing of DL2F FPGA into Xilinx FPGAs. Analyzed the performance of
ATM Adaptation Layer 1 and Forward Error Correction Interface FPGAs.
HONORS, AWARDS AND
PUBLICATIONS
President, Tau Beta Pi Engineering
Member, Eta
Kappa Nu Electrical Engineering Honor Society, 2000-present
R.E. Morgan Memorial Award,
Implementation of a Programmable Phased
Logic Cell, Proceedings of the 45th
IEEE MWSCAS, 2002
RC Extraction of Interconnects at
Sub-Wavelength Dimensions, Artificial
Intelligence and Applications 2005: 491-496
Processor Allocation for Tasks that is
Robust Against Errors in Computation Time Estimates, IPDPS 2005